Synopsys VCS simulation Makefile and commands easy way

VCS Makefile tutorial

Create Makefile where we have to compile and simulate


Compile commands:


For compile verilog file

Command: vcs   top.v


For multiple files create file.list and place all verilog files in order

File.list having file1.v , file2.v etc

Command:   vcs -f file.list  


For system verilog compile we need to pass -sverilog

Command:  vcs -sverilog top.sv

For Class based multiple files create pkg.sv include all sv files in pkg.sv

Pkg.sv contains `include “file1.sv” ,`include “file2.sv.”

EX:
package pkg;

`include “file1.sv”
`include “file2.sv”

endpackage

Command:  vcs -sverilog  +incdir+filespath pkg.sv

Extra attributes in compile command

Sometimes we need  extra attributes in compile time some of them explain below

  • For compile log file   “-l compile.log

         Command: vcs -sverilog -l compile.log top.sv


  • For global time scale which can override all timescales in your files  
          “-timescale_override =1ns/1ps

         Command: vcs -sverilog -timescale_override =1ns/1ps -l compile.log top.sv


  • For local parameter change or set +define+LENGTH=10

            Command:
            vcs -sverilog  +define+LENGTH=10  -timescale_override =1ns/1ps -l compile.log top.sv

  • For uvm users use -ntb_opts  uvm-1.2

          Command:
vcs -sverilog  -ntb_opts uvm-1.2 +define+LENGTH=10  -timescale_override =1ns/1ps -l compile.log top.sv
  • For debug provide “-debug_all”

          Command:
           vcs -sverilog  ntb_opts uvm-1.2  -debug_all +define+LENGTH=10
-timescale_override =1ns/1ps  -l compile.log top.sv

  • For enabling code coverage use “-lca  -cm line+cond+fsm+tgl+assert -cm_tgl mda “

  Command:
           vcs -sverilog  ntb_opts uvm-1.2  -debug_all +define+LENGTH=10
-timescale_override =1ns/1ps  -lca -cm line+cond+fsm+tgl+assert -cm_tgl mda   -l compile.log top.sv
          
         







Simulation commands:

  • Simple file simulation

Command
./simv

  • Simulation with log file

Command
simv -l sim.log

  • Simulation using gui &(waveforms)

Command
 simv  -gui &

Extra attributes in simulation command


  • For uvm use  +UVM_TESTNAME=testname
         Command
         simv +UVM_TESTNAME=testname

  • For code coverage enable use command
           Command
           simv +UVM_TESTNAME=testname -cm line+cond+fsm+tgl+assert -cm_tgl mda

Coverage commands
  •  “urg -dir simv.vdb”  using this command coverage report with default name urgReport.

 “urg  -report user_report  -dir simv.vdb”  uses for username report with user_report

Coverage report

       Using firefox

       Command
       firefox urgReport/grp0.html &